6db6b2ad93266223f3f2cf75230107cfa97fa720
[rtl-433.git] / include / tuner_e4k.h
1 #ifndef _E4K_TUNER_H
2 #define _E4K_TUNER_H
3
4 /*
5  * Elonics E4000 tuner driver
6  *
7  * (C) 2011-2012 by Harald Welte <laforge@gnumonks.org>
8  * (C) 2012 by Sylvain Munaut <tnt@246tNt.com>
9  * (C) 2012 by Hoernchen <la@tfc-server.de>
10  *
11  * All Rights Reserved
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
25  */
26
27 #define E4K_I2C_ADDR    0xc8
28 #define E4K_CHECK_ADDR  0x02
29 #define E4K_CHECK_VAL   0x40
30
31 enum e4k_reg {
32         E4K_REG_MASTER1         = 0x00,
33         E4K_REG_MASTER2         = 0x01,
34         E4K_REG_MASTER3         = 0x02,
35         E4K_REG_MASTER4         = 0x03,
36         E4K_REG_MASTER5         = 0x04,
37         E4K_REG_CLK_INP         = 0x05,
38         E4K_REG_REF_CLK         = 0x06,
39         E4K_REG_SYNTH1          = 0x07,
40         E4K_REG_SYNTH2          = 0x08,
41         E4K_REG_SYNTH3          = 0x09,
42         E4K_REG_SYNTH4          = 0x0a,
43         E4K_REG_SYNTH5          = 0x0b,
44         E4K_REG_SYNTH6          = 0x0c,
45         E4K_REG_SYNTH7          = 0x0d,
46         E4K_REG_SYNTH8          = 0x0e,
47         E4K_REG_SYNTH9          = 0x0f,
48         E4K_REG_FILT1           = 0x10,
49         E4K_REG_FILT2           = 0x11,
50         E4K_REG_FILT3           = 0x12,
51         // gap
52         E4K_REG_GAIN1           = 0x14,
53         E4K_REG_GAIN2           = 0x15,
54         E4K_REG_GAIN3           = 0x16,
55         E4K_REG_GAIN4           = 0x17,
56         // gap
57         E4K_REG_AGC1            = 0x1a,
58         E4K_REG_AGC2            = 0x1b,
59         E4K_REG_AGC3            = 0x1c,
60         E4K_REG_AGC4            = 0x1d,
61         E4K_REG_AGC5            = 0x1e,
62         E4K_REG_AGC6            = 0x1f,
63         E4K_REG_AGC7            = 0x20,
64         E4K_REG_AGC8            = 0x21,
65         // gap
66         E4K_REG_AGC11           = 0x24,
67         E4K_REG_AGC12           = 0x25,
68         // gap
69         E4K_REG_DC1             = 0x29,
70         E4K_REG_DC2             = 0x2a,
71         E4K_REG_DC3             = 0x2b,
72         E4K_REG_DC4             = 0x2c,
73         E4K_REG_DC5             = 0x2d,
74         E4K_REG_DC6             = 0x2e,
75         E4K_REG_DC7             = 0x2f,
76         E4K_REG_DC8             = 0x30,
77         // gap
78         E4K_REG_QLUT0           = 0x50,
79         E4K_REG_QLUT1           = 0x51,
80         E4K_REG_QLUT2           = 0x52,
81         E4K_REG_QLUT3           = 0x53,
82         // gap
83         E4K_REG_ILUT0           = 0x60,
84         E4K_REG_ILUT1           = 0x61,
85         E4K_REG_ILUT2           = 0x62,
86         E4K_REG_ILUT3           = 0x63,
87         // gap
88         E4K_REG_DCTIME1         = 0x70,
89         E4K_REG_DCTIME2         = 0x71,
90         E4K_REG_DCTIME3         = 0x72,
91         E4K_REG_DCTIME4         = 0x73,
92         E4K_REG_PWM1            = 0x74,
93         E4K_REG_PWM2            = 0x75,
94         E4K_REG_PWM3            = 0x76,
95         E4K_REG_PWM4            = 0x77,
96         E4K_REG_BIAS            = 0x78,
97         E4K_REG_CLKOUT_PWDN     = 0x7a,
98         E4K_REG_CHFILT_CALIB    = 0x7b,
99         E4K_REG_I2C_REG_ADDR    = 0x7d,
100         // FIXME
101 };
102
103 #define E4K_MASTER1_RESET       (1 << 0)
104 #define E4K_MASTER1_NORM_STBY   (1 << 1)
105 #define E4K_MASTER1_POR_DET     (1 << 2)
106
107 #define E4K_SYNTH1_PLL_LOCK     (1 << 0)
108 #define E4K_SYNTH1_BAND_SHIF    1
109
110 #define E4K_SYNTH7_3PHASE_EN    (1 << 3)
111
112 #define E4K_SYNTH8_VCOCAL_UPD   (1 << 2)
113
114 #define E4K_FILT3_DISABLE       (1 << 5)
115
116 #define E4K_AGC1_LIN_MODE       (1 << 4)
117 #define E4K_AGC1_LNA_UPDATE     (1 << 5)
118 #define E4K_AGC1_LNA_G_LOW      (1 << 6)
119 #define E4K_AGC1_LNA_G_HIGH     (1 << 7)
120
121 #define E4K_AGC6_LNA_CAL_REQ    (1 << 4)
122
123 #define E4K_AGC7_MIX_GAIN_AUTO  (1 << 0)
124 #define E4K_AGC7_GAIN_STEP_5dB  (1 << 5)
125
126 #define E4K_AGC8_SENS_LIN_AUTO  (1 << 0)
127
128 #define E4K_AGC11_LNA_GAIN_ENH  (1 << 0)
129
130 #define E4K_DC1_CAL_REQ         (1 << 0)
131
132 #define E4K_DC5_I_LUT_EN        (1 << 0)
133 #define E4K_DC5_Q_LUT_EN        (1 << 1)
134 #define E4K_DC5_RANGE_DET_EN    (1 << 2)
135 #define E4K_DC5_RANGE_EN        (1 << 3)
136 #define E4K_DC5_TIMEVAR_EN      (1 << 4)
137
138 #define E4K_CLKOUT_DISABLE      0x96
139
140 #define E4K_CHFCALIB_CMD        (1 << 0)
141
142 #define E4K_AGC1_MOD_MASK       0xF
143
144 enum e4k_agc_mode {
145         E4K_AGC_MOD_SERIAL              = 0x0,
146         E4K_AGC_MOD_IF_PWM_LNA_SERIAL   = 0x1,
147         E4K_AGC_MOD_IF_PWM_LNA_AUTONL   = 0x2,
148         E4K_AGC_MOD_IF_PWM_LNA_SUPERV   = 0x3,
149         E4K_AGC_MOD_IF_SERIAL_LNA_PWM   = 0x4,
150         E4K_AGC_MOD_IF_PWM_LNA_PWM      = 0x5,
151         E4K_AGC_MOD_IF_DIG_LNA_SERIAL   = 0x6,
152         E4K_AGC_MOD_IF_DIG_LNA_AUTON    = 0x7,
153         E4K_AGC_MOD_IF_DIG_LNA_SUPERV   = 0x8,
154         E4K_AGC_MOD_IF_SERIAL_LNA_AUTON = 0x9,
155         E4K_AGC_MOD_IF_SERIAL_LNA_SUPERV = 0xa,
156 };
157
158 enum e4k_band {
159         E4K_BAND_VHF2   = 0,
160         E4K_BAND_VHF3   = 1,
161         E4K_BAND_UHF    = 2,
162         E4K_BAND_L      = 3,
163 };
164
165 enum e4k_mixer_filter_bw {
166         E4K_F_MIX_BW_27M        = 0,
167         E4K_F_MIX_BW_4M6        = 8,
168         E4K_F_MIX_BW_4M2        = 9,
169         E4K_F_MIX_BW_3M8        = 10,
170         E4K_F_MIX_BW_3M4        = 11,
171         E4K_F_MIX_BW_3M         = 12,
172         E4K_F_MIX_BW_2M7        = 13,
173         E4K_F_MIX_BW_2M3        = 14,
174         E4K_F_MIX_BW_1M9        = 15,
175 };
176
177 enum e4k_if_filter {
178         E4K_IF_FILTER_MIX,
179         E4K_IF_FILTER_CHAN,
180         E4K_IF_FILTER_RC
181 };
182 struct e4k_pll_params {
183         uint32_t fosc;
184         uint32_t intended_flo;
185         uint32_t flo;
186         uint16_t x;
187         uint8_t z;
188         uint8_t r;
189         uint8_t r_idx;
190         uint8_t threephase;
191 };
192
193 struct e4k_state {
194         void *i2c_dev;
195         uint8_t i2c_addr;
196         enum e4k_band band;
197         struct e4k_pll_params vco;
198         void *rtl_dev;
199 };
200
201 int e4k_init(struct e4k_state *e4k);
202 int e4k_if_gain_set(struct e4k_state *e4k, uint8_t stage, int8_t value);
203 int e4k_mixer_gain_set(struct e4k_state *e4k, int8_t value);
204 int e4k_commonmode_set(struct e4k_state *e4k, int8_t value);
205 int e4k_tune_freq(struct e4k_state *e4k, uint32_t freq);
206 int e4k_tune_params(struct e4k_state *e4k, struct e4k_pll_params *p);
207 uint32_t e4k_compute_pll_params(struct e4k_pll_params *oscp, uint32_t fosc, uint32_t intended_flo);
208 int e4k_if_filter_bw_get(struct e4k_state *e4k, enum e4k_if_filter filter);
209 int e4k_if_filter_bw_set(struct e4k_state *e4k, enum e4k_if_filter filter,
210                          uint32_t bandwidth);
211 int e4k_if_filter_chan_enable(struct e4k_state *e4k, int on);
212 int e4k_rf_filter_set(struct e4k_state *e4k);
213
214 int e4k_reg_write(struct e4k_state *e4k, uint8_t reg, uint8_t val);
215 uint8_t e4k_reg_read(struct e4k_state *e4k, uint8_t reg);
216
217 int e4k_manual_dc_offset(struct e4k_state *e4k, int8_t iofs, int8_t irange, int8_t qofs, int8_t qrange);
218 int e4k_dc_offset_calibrate(struct e4k_state *e4k);
219 int e4k_dc_offset_gen_table(struct e4k_state *e4k);
220
221 int e4k_set_lna_gain(struct e4k_state *e4k, int32_t gain);
222 int e4k_enable_manual_gain(struct e4k_state *e4k, uint8_t manual);
223 int e4k_set_enh_gain(struct e4k_state *e4k, int32_t gain);
224 #endif /* _E4K_TUNER_H */